The present invention relates to a technique for fetching a branch target instruction in a data processor which is capable of prefetching an instruction, particularly to a technique that is effective in use, for example, for increasing the speed of executing a conditional instruction (instruction executed only when a specific condition is satisfied).
The use of an instruction prefetch technique employing an instruction prefetch buffer and the like will increase the speed of prefetching of an instruction to an instruction register. However, a change in the order of program execution will deprive an instruction, which has been prefetched with great effort, of an opportunity to be executed. The Japanese Patent Application Laid Open No. 7-239781 discloses a technique that judges whether a branch target instruction is stored in an instruction prefetch buffer or not, and which, if it is stored, utilizes the date stored in the instruction prefetch buffer. This technique intends to effectively utilize an instruction once prefetched, even when the instruction execution order of a CPU is changed by a branch target instruction. In addition to this, there are similar techniques disclosed in Japanese Patent Application Laid Open No. 1-239639, No. 2-275532, No. 7-306785, and No. 62-6328.